Large-scale Fabrication of Nanowire Devices
|Semiconductor nanowires (NW) are expected to play a critical role in future electronic and optoelectronic devices as an approach to sustain the scaling trends in electronics and to provide crucial performance enhancements, such as adding photonic functionalities to silicon platforms.|
A technical review by Dr. Sonia Grego , RTI International.
- V.J. Logeeswaran, et al., A 14 ps full width at half maximum high-speed photoconductor fabricated with intersecting InP nanowires on an amorphous surface, Appl. Phys. A, 91 (2008) 1-5. DOI: 10.1007/s00339-007-4394-x
- M.A. Zimmler, et al., Scalable Fabrication of Nanowire Photonic and Electronic Circuits Using Spin-on-Glass, Nano Letters 8 (2008) 1695-1699. DOI: 10.1021/nl080627w
- Z. Fan, et al., Wafer-Scale Assembly of Highly Ordered Semiconductor Nanowire Arrays by Contact Printing, Nano Letters 8 (2008) 20-25. DOI: 10.1021/nl071626r
- Z. Fan, et al., Large-scale, heterogeneous integration of nanowire arrays for image sensor circuitry, PNAS 105 (2008) 11066-11070. DOI:
In recent years, one-dimensional crystalline structures (NW) of various semiconductor materials have been synthesized in large quantities, with controlled and tunable chemical composition and size; functional nanowire devices such as transistors, LED and lasers have been demonstrated. In many studies, devices are obtained by detaching the nanowires from the growth substrate and by placing them on a second substrate from solution dispersions (using methods such as fluidic assembly, self-assembly by Langmuir Blodgett, or dielectrophoresis); placement by dry processes such as transfer printing has recently been reported. Electrical connection is often implemented by defining individual metal contacts with e-beam lithography at the ends of a nanowire after having marked its position, a process that cannot be applied to large scales.
A significant road-block to wide-scale integration of functional NW in integrated circuits is the achievement of a well-defined placement of the NW as well as highly parallel electrical connection to microscale electrodes. In order to be manufacturable, this integration procedure ideally needs to be CMOS-compatibile, accurate, low-cost and scalable to wafer level.
An approach to integration is the use of the nanowire growth substrates themselves for selected placement and connectorization, thereby avoiding the issues of nanowire transfer altogether. A challenge of this approach is the limited selection of growth substrates available for any given semiconductor material. Recently the ability of incorporating crystalline nanowire on non-crystalline surfaces, relaxing lattice matching requirements, was demonstrated by Logesswaran et al .
While device formation on the growth substrate is a promising manufacturing approach, there are applications where nanowire transfer is needed: for example, for the fabrication of pn junction with materials which are not amenable to doping of both types, or for devices on low-temperature substrates (plastic) which are incompatible with the growth process. Two recent papers report on methodologies addressing the issues of highly parallel and scalable fabrication of NW circuits using transfer from the growth substrate.
While the connectorization approach by Zimmler et al is scalable to wafer level, NWs are randomly contacted by metallic lids. On the other hand, this method is compatible with any geometrical arrangement of the NWs and can in principle be combined with an appropriate nanowire placement strategy.
Controlled assembly of aligned NW has been reported with well-defined pitch and high density by a contact printing process in the work from Fan et al . The method involves the directional sliding of a growth substrate consisting of a dense “lawn” of NW on top of a receiver substrate coated with lithographically patterned resist. This transfer, aided by appropriate lubricant and by surface functionalization of the receiving substrate, provides a uniform assembly of both single NW and highly dense parallel arrays, after resist lift off. After the NW placement, source-drain contacts are patterned by photolithography. This method was demonstrated with GeSi NW back-gated FETs in  and more recently by the same group, by developing a CdSe NW optical detector with Ge/Si NW FET amplifier on the same substrate .
These examples of approaches for nanowire integration indicate that the ongoing intense research effort is producing creative solutions and important advances towards manufacturability are being made.
Images from M.A. Zimmler, et al., Scalable Fabrication of Nanowire Photonic and Electronic Circuits Using Spin-on-Glass, Nano Letters 8 (2008) 1695-1699 and Z. Fan, et al., Wafer-Scale Assembly of Highly Ordered Semiconductor Nanowire Arrays by Contact Printing, Nano Letters 8 (2008) 20-25. Reprinted with permission of the American Chemical Society (ACS).
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported.
Login to add your comment.