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Enhanced Performance in Graphene Transistors via Interface Engineering

Written by Jeff Morse, PhD
May 24, 2011
As interest has grown in electronic devices and circuits fabricated from graphene thin films due to the large intrinsic carrier mobility, a key challenge remains to establish device integration strategies that enable field effect transistors (FETs) to have mobility approaching the intrinsic value. With thin film approaches to form graphene using chemical vapor deposition (CVD) on copper foils and subsequent transfer to silicon or other substrates for final integration, graphene has become a prime candidate for a range of applications in very large scale integrated (VLSI) circuits. Recently Liu et. al. have investigated the physics associated with the dielectric-graphene interface for integrated back gated FETs by controlling some of the detrimental scattering effects via application of self-assembled monolayers (SAM). Liu et. al. present a facile approach to improve the performance of scalable graphene transistors utilizing interfacial. The results provide valuable insights into the interfacial physics of graphene FETs. These results ultimately improve the potential application of graphene transistors towards VLSI circuits and applications.


Reviewed by Jeff Morse, PhD, National Nanomanufacturing Network

  • Liu Z, Bol AA, Haensch W. 2011. Large-Scale graphene transistors with enhanced performance and reliability based on interface engineering by phenylsilane self-assembled monolayers. Nano Letters. 2011; 11(2):523-528. doi:10.1021/nl1033842


As interest has grown in electronic devices and circuits fabricated from graphene thin films due to the large intrinsic carrier mobility, a key challenge remains to establish device integration strategies that enable field effect transistors (FETs) to have mobility approaching the intrinsic value. With thin film approaches to form graphene using chemical vapor deposition (CVD) on copper foils and subsequent transfer to silicon or other substrates for final integration, graphene has become a prime candidate for a range of applications in very large scale integrated (VLSI) circuits. Present FET integration approaches employ either bottom-gate designs utilizing a conductive silicon substrate, or a top-gate design. In either embodiment, carrier scattering effects at the dielectric-graphene interface have resulted in limited field effect mobility in comparison to the intrinsic carrier mobility of graphene. Additionally, the presence of mobile and immobile charge defects at the interface, interfacial roughness, and charge injection from the graphene to the dielectric under transient switching excursions result in unfavorable current-voltage (I-V) hysteresis characteristics that impact the reliability and stability of the integrated devices.

(a) A general bottom-gated graphene FET structure with phenyl-SAM interface engineering. (b) Illustration of chemical bonding of the organosilane SAM to the hydroxyl group-enriched dielectric surface. (c) AFM image of a spin-coated ultrasmooth phenyl-SAM with surface roughness of 0.10.2 nm in rms. (d) Microscopy image of a large-area, uniform CVD graphene as patterned to various shapes on a phenyl-SAM engineered silicon oxide wafer (white square areas are metal contacts).
(a) A general bottom-gated graphene FET structure with phenyl-SAM interface engineering. (b) Illustration of chemical bonding of the organosilane SAM to the hydroxyl group-enriched dielectric surface. (c) AFM image of a spin-coated ultrasmooth phenyl-SAM with surface roughness of 0.1~0.2 nm in rms. (d) Microscopy image of a large-area, uniform CVD graphene as patterned to various shapes on a phenyl-SAM engineered silicon oxide wafer (white square areas are metal contacts).
Recently Liu et. al. have investigated the physics associated with the dielectric-graphene interface for integrated back gated FETs by controlling some of the detrimental scattering effects via application of self-assembled monolayers (SAM). Utilizing conductive n-type silicon substrates as the gate electrode, a 300 nm layer of silicon dioxide (SiO2) was thermally grown to serve as the gate dielectric. After wafer cleaning, the SiO2 was subjected to an O2 plasma treatment promoting surface coverage by the hydroxyl group, and subsequently facilitating the growth of organosilane SAM by a simple spin-coating process. Utilizing a 1-1.5:1000 phenyl-silane/anhydrous-toluene solution, the hydroxyl terminated SiO2 surface was spin-coated at 3000 rpm for 1 min. The phenyl-silane reacts immediately with the hydroxyl group and is chemically bonded to the dielectric surface. SAM  polymerization is completed by placing the substrate in a desiccator overnight, then sonicating in toluene, acetone, and isopropanol sequentially to remove any residue. Thin film graphene is grown on a copper foil by CVD at 875C. Transfer of the graphene film to the silicon substrate is achieved by spin-coating a layer of PMMA on the graphene, then dissolving the copper foil in 1 M iron chloride. After rigorously washing the graphene/PMMA layer in DI water, films were transferred to substrates both with and without the phenyl-SAM layer. To complete graphene FET device fabrication, source and drain electrodes were formed using photolithographic patterning and sputter deposition, and the graphene channel was defined by similar patterning and reactive ion etching.

Electrical characterization of FET devices with and without the phenyl-SAM interface treatment exhibited a 150% improvement in extrinsic carrier mobility for the device with the SAM. Furthermore, the I-V characteristics exhibit no hysteresis during the process as the gate voltage is scanned from one polarity to the other, and remains very stable and uniform for devices fabricated over a relatively large area. The authors further analyzed the I-V characteristics for devices with and without the phenyl-SAM, applying models previously developed to predict the Dirac point shift during the voltage sweep. From this analysis the authors attributed the enhanced carrier mobility to reduced interfacial impurity and surface polar phonon scattering as well as the ultra-smooth SAM surface. The authors further found that the hysteresis present in devices without the interface treatment at room temperature was dominated by charge injection from the grahene to the graphene-dielectric interface. This finding was further supported by the Dirac point shift model results.

Thus a facile approach to improve the performance of scalable graphene transistors utilizing interfacial engineering has been reported. The results further provide valuable insights into the interfacial physics of graphene FETs. These results ultimately improve the potential application of graphene transistors towards VLSI circuits and applications.

 

Figure reprinted with permsision from Liu Z, Bol AA, Haensch W. 2011. Large-Scale graphene transistors with enhanced performance and reliability based on interface engineering by phenylsilane self-assembled monolayers. Nano Letters. 2011; 11(2):523-528. doi:10.1021/nl1033842. Copyright 2011 American Chemical Society.

Last updated: May 30, 2014
 

DOI: 10.4053/er527-110525

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Tags: Graphene, Transistors, dielectric-graphene interface, FET, phenylsilane self-assembled monolayers, silicon dioxide, spin-coating, Thin films, Chemical vapor deposition (CVD), PMMA, Photolithography, Reactive ion etching

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