Graphene has been attracting considerable interest in recent years as a result of its unique band structure and physical properties, including extremely high carrier mobility, that make it a promising material for the semiconductor industry, though not one without challenges. One issue to consider has been the methods used to produce graphene films, including exfoliated graphite which yields graphene sheets sufficient only for research studies. Recent approaches to large-area synthesis of high quality single layer and multilayer graphene films have been explored by thermal decomposition of single crystal silicon carbide and chemical vapor deposition (CVD) on single crystal transition metals. While these approaches represent a significant step towards scaled production of quality graphene films, the requirements of high vacuum processing and expensive substrates with limited size still fall short of an integrated approach to incorporate this materials system.
Graphene films transferred onto a SiO2/Si substrate. In 2009, Li et. al. reported on the large-area synthesis of graphene using atmospheric pressure CVD on copper foils using a methane feed. The films grow on the copper via a surface-catalyzed process which effectively self-limits the film growth resulting in predominantly (>95%) monolayer graphene films with limited areas of multilayer graphene flakes. The deposited films are continuous across the foil surface, and can be readily transferred to other substrates using a repeatable, facile method suitable for a range of substrates, including silicon and glass. The authors further note that the graphene film thickness is not dependent upon the initial copper foil thickness or deposition time, leading to the conclusion that the process is driven by a surface-catalysis effect, and is therefore self-limiting. Subsequent evaluation of the electrical properties of the graphene films utilized dual gate field effect transistor (FET) devices fabricated using an aluminum oxide gate dielectric. The resulting performance of the transistors indicated a carrier mobility on the order of 4050 cm^2/V-sec, suggesting reasonable material quality but less than previous results demonstrated for exfoliated graphene. Clear advantages of this approach include the scalability to readily available silicon wafer scale processing tool sets, and the ability to transfer the films for integration within existing semiconductor fabrication methodologies.
The atomic structure of graphene. (a) Artist view of a single layer of graphene on top of a nickel (111) surface, the other figures present STM images of different types of graphene. (b) Few layer exfoliated graphene. (c) Single layer of exfoliated graphene. (d) Graphene single layer produced by the process described in this work. More recently, Hofrichter et.al. reported on the synthesis of graphene films directly on oxidized silicon substrates using a solid carbon (SiC) source. Using a silicon substrate with 300nm silicon dioxide as the starting material, the authors deposited via plasma enhanced chemical vapor deposition (PECVD) a 50 nm film of silicon carbide , followed with a 500nm film of nickel (Ni) by dc magnetron sputtering. The films are then annealed in nitrogen at 1100 degrees C for 30 seconds by rapid thermal anneal (RTA), during which the SiC dissolves within the Ni film. Upon cooling the carbon segregates to the Ni surface forming a graphene layer. Of critical importance are the initial SiC and Ni film thickness, which must be sufficient to achieve a continuous graphene film while completely dissolving the original SiC layer. In addition the film must leave a substoichiometric nickel silicide that can be readily etched away with less aggressive chemistries such as nitric acid for subsequent graphene film transfer and processing. Materials characterization exhibited large regions of monlayer graphene mixed in with multilayer graphene, indicating that additional investigations are necessary to optimize the process for achieving large area, predominantly monolayer films. The authors fabricated resistor structures by selectively removing the Ni-silicon layer and allowing the graphene film to settle onto the silicon dioxide. Electrodes were then deposited and patterned on the graphene, with electrical characterization measuring the modulation effects of the current transport through the graphene films by a back gate electrode formed on the silicon. Thus, while the materials properties and uniformity demonstrated in this work has room for improvement, this method has potential advantages from a materials synthesis and process integration approach.
