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Carbon Nanotube Thin Film Transistors—Ready for Prime Time?

Written by: 
Jeff Morse, PhD.

Wang Figure 1F
Thin film transistors (TFT) have gained interest as switching devices for large area displays and, more recently, for a range of large area flexible substrate applications. While much TFT development has focused on amorphous silicon, the expensive vacuum processing and low carrier mobility associated with these systems have prompted researchers to explore alternative materials. Organic TFTs, for example, have also received significant attention but also suffer from relatively low device mobility.

Recent efforts to synthesize carbon nanotube networks in a transistor integration strategy have shown significant promise as an alternative technology for large area TFT applications. With new knowledge of necessary process control mechanisms and carbon nanotube network properties, these approaches use solution-based assembly techniques to achieve specific device parameters by design and have the potential to gain a foothold in a high-end consumer products markets.

Single walled carbon nanotubes (SWCNT) have gained significant attention over the past decade due to potentially superior electronic, mechanical, and chemical properties. For nanoelectronic applications, transistors fabricated from individual SWCNTs exhibit very high carrier mobility, yet have limited current carrying ability due to their nanoscale size.  Furthermore, practical approaches to fabricate large scale integrated circuits have not yet been realized. In contrast, TFT applications simply require sufficient device characteristics (On/Off ratio, on-state conductance, and carrier mobility) in a thin, nominally transparent design configuration and can be fabricated by low-cost, scalable processes. Progress in device synthesis has been limited by the chirality properties of the SWCNT networks, which typically contain a mixture of semiconducting and metallic CNTs. As the SWCNTs are assembled in an overlapping configuration between the source and drain of the transistor,  percolation transport through metallic nanotubes limits the device on/off ratio, yet enables high current handling capability. Rigorous purification processes have been used to yield SWCNT networks composed primarily of semiconducting nanotubes.

A handful of studies published within the last year have focused on the process of integrating SWCNT networks into TFTs with very positive outcomes for industrial scale up. The knowledge gained from this nanomanufacturing research has provided sufficient progress suggesting these approaches may be suitable for rigorous process scale-up for specific applications. With key metrics for TFT devices being demonstrated, applications realizing an immediate benefit from this manufacturing approach include displays, lighting, and electronic paper. This month we take a closer look at three key papers in this area that have fostered significant interest within the community.

Engel Figure 3
(a) CNT-TFT device schematic. (b) SEM micrograph of a typical device.
Engel et. al. from IBM employed density gradient ultracentrifugation to achieve 99% enriched semiconducting nanotubes. Dispersing the purified SWCNTs in an aqueous solution containing 1% sodium dodecyl sulfate (SDS), an evaporative-driven self-assembly process was used to create aligned CNT networks forming a thin film aligned to the source and drain of a TFT. Gate structures were fabricated with  lengths ranging from 0.5 to 10 µm. Depending on the density of the SWCNTs in the thin film and the transistor gate length, the fundamental tradeoff between on-state conduction and on/off ratio was overcome. The authors reported on/off ratios of 10^3-10^4, on state currents of 10 µA and carrier mobility of 5-20 cm^2/V-sec for the range of gate lengths fabricated.

Wang Figure 2a
Schematic diagram of a back-gated transistor built on separated nanotube thin-film with Ti/Pd (5 Å/70 nm) contacts and SiO2 (50 nm) gate dielectric
Even more recently, Wang et. al. from the University of Southern California, and LeMieux et. al. from Stanford University demonstrated a facile solution-based assembly process for fabricating CNT networks over large areas. In the approach reported by these groups, aminosilane is introduced to the assembly process due to its well known affinity to carbon nanotubes. The silicon/silicon dioxide surface was first functionalized with aminopropyltriethoxy silane (APTES) forming an amine-terminated monolayer in the silicon dioxide surface. The wafer was then immersed in (Wang et. al.) or spin coated with (LeMieux et. al.) a dilute aqueous solution containing the purified semiconducting SWCNTs and SDS. Results of these studies showed that the density of the SWCNT network deposited exhibited a dependency on the concentration of CNTs in the dispersion and the length of time the substrate was exposed to the suspension or associated spin-coating parameters. Interestingly, the USC group in their approach used only 95% purity semiconducting nanotubes with an average length of 1.7 µm. Using this technique, 3 inch wafer scale fabrication of SWCNT TFT devices  had better then 98% yield, low sheet resistance (25 KΩ/sq), high current density (~10 µA/µm), good on/off ratio (>10^4), and high mobility (~52 cm2/V-sec). These results demonstrate sufficient performance benefits over alternative TFT technologies. So much sothat the facile solution-based assembly method described above offers a practical technique for scaled nanomanufacturing platforms.

It should be acknowledged that the findings of each of the investigations cited abovehave provided critical insights into the physics and phenomenon of current transport in mixed chirality CNT networks providing the basis for developing transistor design strategies conducive to large area TFT applications. With this emphasis, the nanomanufacturing community will look forward to future commercialization of this technology.

  1. Engel M, Small JP, Steiner M, Freitag M, Green AA, Hersam MC, and Avouris P. 2008. Thin Film Nanotube Transistors Based on Self-Assembled, Aligned, Semiconducting Carbon Nanotube Arrays. ACS Nano 2 (12): 2445–2452. DOI: 10.1021/nn800708w.
  2. LeMieux MC, Sok S, Roberts ME, Opatkiewicz JP, Liu D, Barman SN, Patil N, Mitra S, and Bao Z. Solution Assembly of Organized Carbon Nanotube Networks for Thin-Film Transistors. ACS Nano, Article ASAP 19 November 2009. DOI: 10.1021/nn900827v.
  3. Wang C, Zhang J, Ryu K, Badmaev A, Gomez De Arco L, and Zhou C. 2009. Wafer-Scale Fabrication of Separated Carbon Nanotube Thin-Film Transistors for Display Applications. Nano Letters 9 (12): 4285–4291. DOI: 10.1021/nl902522f.  

Images reproduced with permission from Wang C, et al. Nano Letters 9 (12): 4285–4291 and Engel M, et al. ACS Nano 2 (12): 2445–2452. Copyright 2009/8 American Chemical Society.