Skip to main content
Home

Directed Assembly of Carbon Nanotubes: Facilitating Seamless Integration with Future Generation Nanoelectronics

November 12, 2008
Researchers at Northeastern University report a scalable method for directed assembly of single-wall carbon nanotubes at ambient temperatures for application with integrated circuits.

 

Reviewed by Jeff Morse, PhD., National Nanomanufacturing Network

As future generation electronics strive to increase the density of transistors on a semiconductor chip through continued reduction of feature size, a number of critical barriers are being encountered, including the capacity of the metallic interconnects to carry and distribute current, and the resulting heat dissipation from resistive losses in these interconnects. Single wall carbon nanotubes (SWNT) have become one of the most studied and characterized structures in nanoscale science today, predominantly due to the unique electronic properties which include extremely high conductivity and electron mobility. Combining these properties with the ability to render the SWNT either metallic or semiconducting sets the stage for a new paradigm for design of integrated circuits in which nanoscale wiring is achieved through precision layout and configuration of SWNT elements on an integrated circuit chip.

CNT arrays
SEM micrographs of assembled SWNT arrays (a) top and (b) cross-sectional.

While it has been shown that the positioning and direction of carbon nanotubes (CNT) can be controlled during growth, these methods typically require high temperature synthesis processes that are not conducive with semiconductor integrated circuits. Furthermore, growth of CNT onto devices must address the additional challenges of size distribution, contamination, and positioning with nanometer precision. The latter can be addressed through post-process steps including cleaning, cutting, and sorting to achieve narrow size and length distributions, along with chemical functionality to control surface and electronic properties. Having control of the post-process parameters for bulk manufactured SWNT have spawned studies on post-synthesis assembly methods including physical manipulation, surface functionalization, magnetic and electric field assisted assembly, and transfer printing. The key to any of post-synthesis assembly process is scalability to large areas.

Recently, a group at Northeastern University has demonstrated the directed assembly of SWNT into nanotemplated arrays formed on silicon substrates using electrophoresis and dielectrophoresis at ambient temperatures. Nanotemplates were formed by standard anodic aluminum oxide methods in which a 1 µm thin film of aluminum is converted into a porous alumina film via the anodization process. The resulting alumina film has a high density of vertically aligned pores having diameters on the order of <40 nm. Variations on the anodization process parameters can further control pore diameter, spacing, and periodicity. Once the nanotemplates are formed, the silicon substrate is then immersed into a solution containing negatively charged SWNT, and an electrode is attached to the backside of the silicon substrate with a negatively biased counter electrode positioned over the nanotemplated surface. Applying both 10 V DC and 10V AC at 1 MHz to the counter electrode, in this case a Pt-Ir wire at a precisely positioned height above the nanotemplates, the electric field strength is sufficient to orient the nanotubes in the solution and literally thread the individual nanotubes into nanotemplates as the counter electrode wire is scanned over the nanotemplates. While some of the assembled SWNT remained in bundles, the majority were individual SWNT positioned vertically in the anodized aluminum oxide nanotemplate. Subsequent electrical testing was achieved by coating the top surface of the alumina with gold thereby interconnecting the SWNT at the top surface. Electrical measurements exhibited both improved conductivity compared to bulk thin film metals, as well as rectification properties as the polarity of the applied bias is changed.

While issues remain to be studied for further feasibility and scaling in order to integrate SWNT with future generation electronics, this work demonstrates a method that is clearly scalable and compliant with semiconductor integrated circuits. The ability to precisely control the properties of SWNT through post-synthesis procedures, and subsequently position individual SWNT in three dimensions with nanometer precision represents an enabling method for seamless manufacturing and integration of advanced nanoelectronics.

See also: Nanotechwire and Physorg.

Image reproduced from Gultepe, E., et al. Large scale 3D vertical asembly of single-walled carbon nanotubes at ambient temperatures. Nanotechnology 19 (2008) with permission from IOP and the authors. 

 

Last updated: October 01, 2009
 

DOI: 10.4053/er143-081112

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported.

Tags: Carbon nanotube (CNT), Semiconductors, Integrated Circuits, Directed Assembly

Previous   Next