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Wafer-scale Fabrication of CMOS Logic by Aligned Arrays of Single-wall Carbon Nanotubes

March 16, 2009
Ryu and colleagues report the fabrication of SWNT integrated circuits over a large area (4” wafer) and with superior performance using a horizontal array of aligned, non-overlapping nanotubes with lithographically patterned electrical contacts for a group of nanotubes.

 

Reviewed by Sonia Grego, Ph.D., RTI International

The interest in developing electronic devices based on single-wall carbon nanotubes (SWNT) derives from the promise of higher performance than silicon-based CMOS (complementary metal-oxide semiconductor) integrated circuits (IC), which are at the heart of the microelectronics industry. While many studies have been performed to evaluate the performance of SWNT integrated circuits with proof-of-concept fabrication approaches [1], device fabrication needs to be implemented at a wafer-scale in order to be of industrial interest.

Among the challenges to fabricate SWNT devices at a wafer-scale are the difficulty of synthetizing carbon nanotubes with controlled chirality and therefore controlled transport properties and the accurate positioning and electrical addressing of a large number of nanotubes. The idea at the core of Ryu and colleagues' recently-published report (Ryu et al 2009.) is the use of a horizontal array of aligned, non-overlapping nanotubes with lithographically patterned electrical contacts for a group of nanotubes. This type of approach has been implemented previously by this and other groups (see for example [2, 3]). This paper describes advances obtained in multiple fabrication steps, below, which enable the implementation of advanced electronic logic functions at a full 4” wafer scale. 

  1. A massively parallel growth of aligned nanotubes on a 4” wafer was achieved by controlled chemical vapor deposition synthesis on suitable epitaxial substrates (sapphire or quartz). The geometrical alignment was achieved by patterning the growth catalyst on the substrate. This growth mechanism however, does not control the chirality of the nanotubes and approximately 30% of them are metallic.
  2. Wafer-level transfer of the SWNT from the growth wafer to a thermal oxide silicon wafer was performed using a thermal-tape-based procedure developed by this group of investigators. The transfer step enabled the devices to be processed on a silicon substrate highly suited for IC fabrication and to re-use expensive growth substrates. As expected, the growth and transfer processes do produce a certain number of defects and misalignments, as illustrated by efforts to implement defect-tolerant logic circuit designs.
  3. Source and drain contacts for the transistors were then patterned using standard CMOS procedure. In this specific work, high resolution stepper photolithography enabled patterning of very short submicron channels, which improves performance and is line with industry trends. Both common bottom gate and top gate configurations were implemented.
  4. After patterning of the contacts, a controlled electrical breakdown was performed which essentially consists of driving a large current through the nanotubes to "burn out" the metallic ones and leave behind the semiconductor ones required by the transistor operation.
  5. Ryu Figure 4
    PMOS NOR and NAND gates with top-gated transistors. Examples of defect tolerant designs are b) and c).
    A key element for the popularity of CMOS electronics is its very low-power consumption which is enabled by a circuit configuration using both p-doped and n-doped semiconductors. Therefore, in order to obtain CMOS-analogous low power operation, SWNT must be doped both positively and negatively. While p-doping is easily achieved (and pMOS logic widely reported in the literature), n-doping has been the object of intense investigation by these and other authors and it has been revealed to be rather unstable in air. The method used in this work to obtain nMOS was potassium doping. 
  6. Devices were fabricated with defect tolerant designs such as the one for two transistors controlled by gates A and B which are connected in parallel and utilize the same bunch of aligned NT. Their graphic (right) illustrates the design and the result of implementation of logic NOR and NAND according to the design of gates A and B. The NOR output is zero, when either of the inputs is 1; the NAND output is 1 when either (or both) of the inputs is zero. The design of figure 1c ensures identical performance of transistors as long as they use the same group of a few SWNT. It must be observed however that such a design does not help with devices using a neighboring and different group of SWNT. 

With respect to previous papers on CMOS logic implemented with arrays of SWNT, this article reports fabrication over a large area (4” wafer) and a superior performance. However, the performance, as illustrated by parameters such as mobility µ~3000 cm2/Vs, is at least an order of magnitude lower than the experimental values reported in single-device fabrication papers as well as the theoretical limit [4]. The reported performance is higher than the mobility of traditional Si CMOS (typically  hundreds cm2/Vs), however, competing emerging technologies such as strained  SiGe and GaAs MOSFET are reporting mobilities in excess of 5000 cm2/Vs [5]. Whether SWNT integrated circuits will achieve the performance, reliability, and process uniformity required to be attractive for future beyond-silicon electronics applications remains a challenge.

References

[1]     Javey A, Guo J, Wang Q, Lundstrom M, and Dai, H. 2003. Ballistic carbon nanotube field-effect transistors. Nature 424: 654-657.
[2]     Javey A, Wang Q, Ural A, Li Y and Dai H. 2002. Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring Oscillators. Nano Letters 2: 929-932.
[3]     Kang SJ, Kocabas C, Ozel T, Shim M, Pimparkar N, Alam M, Rotkin S, and Rogers JA. 2007. High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes. Nature Nanotechnology 2: 230-236.
[4]     Zhou X, Park JY, Huang S, Liu J, and McEuen PL. Band Structure, Phonon Scattering, and the Performance Limit of Single-Walled Carbon Nanotube Transistors. Physical Review Letters 95: 146805.
[5]     Passlack M, Droopad R, Thayne I, and Asenov A. III-V MOSFETs for future CMOS transistor applications. Solid State Technology [Internet]. Available from:  http://www.solid-state.com/display_article/346921/5/none/none/Feat/III-V-MOSFETs-for-future-CMOS-transistor-applications.

Image reproduced with permission from Ryu K, Badmaev A, Wang C, Lin A, Patil N, Gomez L, Kumar A, Mitra S, Wong HSP, Zhou C. 2009. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer device and integrated circuits using aligned nanotube. Nano Letters 9(1):189-197. Copyright 2009 American Chemical Society.

Last updated: June 13, 2014
 

DOI: 10.4053/er182-090316

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Tags: CMOS, Nanoelectronic circuits and architectures, Integrated Circuits, Carbon nanotubes

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